1. Field of the Invention
This invention relates generally to the field of semiconductor devices, and more particularly, to a dielectric layer structure and a method of manufacturing the same.
2. Description of the Related Art
With each generation of metal oxide semiconductor (MOS) integrated circuit (IC), the device dimensions have been continuously scaled down to provide for high-density and high-performance devices. Particularly, the thickness of gate dielectrics is made as small as possible because the drive current in a MOS field effect transistor (FET) increases with decreasing gate dielectric thickness. Thus, it has become increasingly important to provide extremely thin, reliable, and low-defect gate dielectrics for improving device performance.
For decades, a thermal oxide layer, e.g. silicon dioxide (SiO2), has been used as the gate dielectrics because the silicon dioxide thermal oxide layer is stable with the underlying silicon substrate and the fabrication process is relatively simple.
However, because the silicon dioxide gate dielectrics has a low dielectric constant (k), e.g., 3.9, further scaling down of silicon dioxide gate dielectric thickness has become more and more difficult, especially due to gate-to-channel leakage current through thin silicon dioxide gate dielectrics.
This leads to consideration of alternative dielectric materials that can be formed in a thicker layer than silicon dioxide but still produce the same or better device performance. The performance can be expressed as “equivalent oxide thickness (EOT).”
This is mainly because the physically thicker metal oxide can reduce gate-to-channel leakage current while the device performance is not adversely impacted. Further, if the dielectric layer can be made sufficiently thick, etching margin can be increased during the patterning of gate stacks. This increased etching margin prevents the silicon substrate from being exposed by the etching process for patterning the gate stacks.
To this end, a high-k (high dielectric constant) metal oxide materials have been proposed as the alternative dielectric materials for gate or capacitor dielectrics. Because the dielectric constant of a metal oxide material can be made greater than that of the silicon dioxide, a thicker metal oxide layer having a similar EOT can be deposited.
Unfortunately, the use of high-k metal oxide materials presents several problems when using traditional substrate materials such as silicon. The silicon can react with the high-k metal oxide or oxidize during deposition of the high-k metal oxide or subsequent thermal processes, thereby forming an interface layer of silicon dioxide. This increases the equivalent oxide thickness, thereby degrading device performance.
Further, an interface trap density between the high-k metal oxide layer and the silicon substrate is increased. Thus, the channel mobility of the carriers is reduced. This reduces the on/off current ratio of the MOS transistor, thereby degrading its switching characteristics.
Also, the high-k metal oxide layer such as a hafnium oxide (HfO2) layer or a zirconium oxide (ZrO2) layer has a relatively low crystallization temperature and is thermally unstable. Thus, the metal oxide layer can be easily crystallized during a subsequent thermal annealing process for activating the impurities injected into source/drain regions. This can form grain boundaries in the metal oxide layer through which current can pass. And the surface roughness of the metal oxide layer increases, deteriorating the leakage current characteristics. Further, the crystallization of the high-k metal oxide layer undesirably affects a subsequent alignment process due to irregular reflection of the light on an alignment key having the rough surface.
Various attempts have been made to address the above-mentioned problems. For example, U.S. Pat. No. 6,020,024 discloses an oxynitride layer interposed between a silicon substrate and a high-k dielectric layer. U.S. Pat. No. 6,013,553 discloses a zirconium oxynitride layer or a hafnium oxynitride layer as the gate dielectrics. Further, PCT International Patent Application Publication No. WO 00/01008 discloses SiO2, silicon nitride and oxynitride interface layers. Also, U.S. Pat. No. 6,020,243 discloses a high permittivity zirconium (or hafnium) silicon-oxynitride gate dielectrics.
However, such methods have not succeeded in solving the above-mentioned problems. For example, the silicon nitride layer or oxynitride layer between the high-k dielectric layer and the silicon substrate or the polysilicon gate electrode causes charge trapping with high interface state densities. Thus, such methods reduce channel mobility and degrade device performance. Further, the formation of the silicon nitride layer or the oxynitride layer requires a relatively large thermal budget.
Importantly, in the case of the silicon nitride layer, because the dielectric constant of silicon nitride is only about 1.5 times greater than that of silicon dioxide, it has been difficult to reduce an EOT, thus inhibiting the improvements in device performance.
Accordingly, a need still remains for an improved dielectric layer structure with a higher crystallization temperature and the method of manufacturing the same to improve the device performance by reducing the equivalent oxide thickness of the dielectric layer as well as improvement of the interface characteristics.